diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index aefa9fc..afdb747 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -19,20 +19,20 @@
 #include <asm/hardware.h>
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
 
 /* SDRAM */
 #define CFG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
 #define CFG_SYS_SDRAM_SIZE		0x04000000
 
-#define CONFIG_SYS_INIT_RAM_SIZE	(16 * 1024)
-#define CONFIG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE	(16 * 1024)
+#define CFG_SYS_INIT_RAM_ADDR	ATMEL_BASE_SRAM1
 
 /* NOR flash, if populated */
 #ifdef CONFIG_SYS_USE_NORFLASH
 #define PHYS_FLASH_1				0x10000000
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CFG_SYS_FLASH_BASE			PHYS_FLASH_1
 
 /* Address and size of Primary Environment Sector */
 
@@ -50,9 +50,9 @@
 #define MASTER_PLL_OUT		3
 
 /* clocks */
-#define CONFIG_SYS_MOR_VAL						\
+#define CFG_SYS_MOR_VAL						\
 		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
-#define CONFIG_SYS_PLLAR_VAL					\
+#define CFG_SYS_PLLAR_VAL					\
 	(AT91_PMC_PLLAR_29 |					\
 	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
 	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
@@ -60,31 +60,31 @@
 	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
 
 /* PCK/2 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR1_VAL		\
+#define	CFG_SYS_MCKR1_VAL		\
 	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
 	 AT91_PMC_MCKR_MDIV_2)
 
 /* PCK/2 = MCK Master Clock from PLLA */
-#define	CONFIG_SYS_MCKR2_VAL		\
+#define	CFG_SYS_MCKR2_VAL		\
 	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |	\
 	AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+#define CFG_SYS_PIOD_PDR_VAL1	0xFFFF0000
 /* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+#define CFG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL					\
+#define CFG_SYS_MATRIX_EBICSA_VAL					\
 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
 	 AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1		0
+#define CFG_SYS_SDRC_MR_VAL1		0
 /* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+#define CFG_SYS_SDRC_TR_VAL1		0x13C
 /* SDRAMC_CR - Configuration register*/
-#define CONFIG_SYS_SDRC_CR_VAL							\
+#define CFG_SYS_SDRC_CR_VAL							\
 		(AT91_SDRAMC_NC_9 |						\
 		 AT91_SDRAMC_NR_13 |						\
 		 AT91_SDRAMC_NB_4 |						\
@@ -98,10 +98,10 @@
 		 (1 << 28))		/* Exit Self Refresh to Active Delay */
 
 /* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CFG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CFG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
 #define CFG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CFG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
 #define CFG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
 #define CFG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
 #define CFG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
@@ -110,35 +110,35 @@
 #define CFG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
 #define CFG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
 #define CFG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CFG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
 #define CFG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CFG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
 #define CFG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CFG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
 #define CFG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL				\
+#define CFG_SYS_SMC0_SETUP0_VAL				\
 	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
 	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL				\
+#define CFG_SYS_SMC0_PULSE0_VAL				\
 	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
 	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+#define CFG_SYS_SMC0_CYCLE0_VAL	\
 	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL				\
+#define CFG_SYS_SMC0_MODE0_VAL				\
 	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
 	 AT91_SMC_MODE_DBW_16 |					\
 	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL			\
+#define CFG_SYS_RSTC_RMR_VAL			\
 		(AT91_RSTC_KEY |		\
 		AT91_RSTC_MR_URSTEN |		\
 		AT91_RSTC_MR_ERSTL(15))
 
 /* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL				\
+#define CFG_SYS_WDTC_WDMR_VAL				\
 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
 		 AT91_WDT_MR_WDV(0xfff) |			\
 		 AT91_WDT_MR_WDDIS |				\
@@ -160,6 +160,6 @@
 #endif
 
 /* USB */
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CFG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
 
 #endif